FIG. 1 shows a lay-out of a conventional semiconductor memory device. A word line 100 is arranged perpendicularly to an active region 200. A contact hole 300 for a lower capacitor electrode and a contact hole 400 for a bit line are each formed between word lines. During formation of the contact holes 300 and 400, misalignment can cause deviation of the contact holes from active regions 200. Because of such deviation, a silicon substrate 1 can be over-etched more than necessary during the formation of the contact holes 7 and 7a (i.e., during etching of a very thick interlayer insulating layer 5) as shown by dotted circles A and A' of FIGS. 2 and 3. If the over-etching reaches a well region (e.g., silicon region) of silicon substrate 1, a lower capacitor electrode or a bit line to be formed by following process steps is short-circuited with the well region. In addition, leakage currents can be increased because of the over-etching.
Accordingly, a need remains for a method for forming contact holes without causing the over-etching problem.